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TMS320C6701

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C67x floating-point DSP- up to 167MHz, McBSP

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Data sheet
Errata

TMS320C6701

ACTIVE
Data sheet Order now

Product details

DSP type 1 C67x DSP (max) (MHz) 150, 167 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 90
DSP type 1 C67x DSP (max) (MHz) 150, 167 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 90
FCBGA (GJC) 352 1225 mm² 35 x 35
  • Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701
    • 8.3-, 6.7-, 6-ns Instruction Cycle Time
    • 120-, 150-, 167-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1 GFLOPS
    • TMS320C6201 Fixed-Point DSP Pin-Compatible
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x™ CPU Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision Instructions
    • Hardware Support for IEEE Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 1M-Bit On-Chip SRAM
    • 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
    • 512K-Bit Dual-Access Internal Data (64K Bytes)
  • 32-Bit External Memory Interface (EMIF) to Synchronous/Asynchronous Memories
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • 52M-Byte Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 352-Pin Ball Grid Array (BGA) Package (GJC Suffix)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
  • 3.3-V I/Os, 1.9-V Internal (167-MHz Only)

VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.
  • Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701
    • 8.3-, 6.7-, 6-ns Instruction Cycle Time
    • 120-, 150-, 167-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1 GFLOPS
    • TMS320C6201 Fixed-Point DSP Pin-Compatible
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x™ CPU Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision Instructions
    • Hardware Support for IEEE Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 1M-Bit On-Chip SRAM
    • 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
    • 512K-Bit Dual-Access Internal Data (64K Bytes)
  • 32-Bit External Memory Interface (EMIF) to Synchronous/Asynchronous Memories
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • 52M-Byte Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 352-Pin Ball Grid Array (BGA) Package (GJC Suffix)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
  • 3.3-V I/Os, 1.9-V Internal (167-MHz Only)

VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000™ DSP platform. The TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000™ DSP platform. The TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
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Technical documentation

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Type Title Date
* Data sheet TMS320C6701 Floating-Point DSP datasheet (Rev. F) 01 Mar 2004
* Errata TMS320C6701 Silicon Errata (Rev. A) 31 Jan 2001
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 May 2021
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 02 Jul 2009
Application note TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 04 Sep 2007
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20 May 2007
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11 Apr 2007
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 14 Dec 2006
User guide TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide (Rev. A) 07 Nov 2006
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 01 Jan 2006
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 01 Mar 2005
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25 Jan 2005
User guide TMS320C620x/C670x DSP Program & Data Memory Controller/DMA Controller Ref.Guide (Rev. A) 03 Sep 2004
User guide TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 13 Aug 2004
Application note TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 26 Apr 2004
Application note TMS320C6000 Board Design: Considerations for Debug (Rev. C) 21 Apr 2004
Application note TMS320C6000 McBSP Initialization (Rev. C) 08 Mar 2004
User guide TMS320C6000 DSP Interrupt Selector Reference Guide (Rev. A) 09 Jan 2004
User guide TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 31 Jul 2003
User guide TMS320C620x/C670x DSP Boot Modes and Configuration Reference Guide 31 Jul 2003
Application note How to Begin Development Today w/ High Performance Floating Point TMS320C67x DSP 23 Apr 2003
Application note Using IBIS Models for Timing Analysis (Rev. A) 15 Apr 2003
User guide TMS320C6201/6701 Evaluation Module User's Guide (Rev. F) 13 Aug 2002
Application note TMS320C62x/C67x Power Consumption Summary (Rev. C) 30 Jul 2002
Application note TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 04 Jun 2002
Application note TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 17 Apr 2002
Application note TMS320C6000 DMA Example Applications (Rev. A) 10 Apr 2002
Application note TMS320C6000 Board Design for JTAG (Rev. C) 02 Apr 2002
Application note TMS320C6000 Memory Test (Rev. A) 19 Feb 2002
Application note TMS320C6000 EMIF to External Flash Memory (Rev. A) 13 Feb 2002
Application note Using a TMS320C6000 McBSP for Data Packing (Rev. A) 31 Oct 2001
Application note Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 30 Sep 2001
Application note TMS320C6000 Host Port to MC68360 Interface (Rev. A) 30 Sep 2001
Application note TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 31 Aug 2001
Application note TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 31 Aug 2001
Application note Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 31 Aug 2001
Application note TMS320C6000 System Clock Circuit Example (Rev. A) 15 Aug 2001
Application note TMS320C6201/6701 EVM: TMS320C6000 McBSP to Multimedia Audio Codec (Rev. A) 24 Jul 2001
Application note TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 23 Jul 2001
Application note TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 10 Jul 2001
Application note TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 30 Jun 2001
Application note TMS320C6000 Host Port to MPC860 Interface (Rev. A) 21 Jun 2001
Application note TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 21 May 2001
Application note Circular Buffering on TMS320C6000 (Rev. A) 12 Sep 2000
Application note TMS320C6000 McBSP as a TDM Highway (Rev. A) 11 Sep 2000
Application note TMS320C620x/TMS3206701 DMA and CPU: Data Access Performance (Rev. A) 16 Aug 2000
Application note TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 02 Feb 2000
Application note TMS320C6000 C Compiler: C Implementation of Intrinsics 07 Dec 1999
Application note TMS320C6000 McBSP: I2S Interface 08 Sep 1999

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