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Digital signal processors (DSPs)

TMS320C6671

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High performance single-core C66x fixed and floating-point DSP - 1GHz

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Data sheet
Errata

TMS320C6671

ACTIVE
Data sheet Order now

Product details

DSP type 1 C66x DSP (max) (MHz) 1000, 1250 CPU 32-/64-bit Operating system DSP/BIOS Security Crypto accelerators Ethernet MAC 2-Port 1Gb switch PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
DSP type 1 C66x DSP (max) (MHz) 1000, 1250 CPU 32-/64-bit Operating system DSP/BIOS Security Crypto accelerators Ethernet MAC 2-Port 1Gb switch PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (CYP) 841 576 mm² 24 x 24
  • One TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.25GHz
    • 40 GMAC/20 GFLOP @ 1.2GHz
    • 32KB L1P, 32KB L1D, 512KB L2
    • 1 MB Shared L2
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessors- Packet Accelerator, Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
  • 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
  • 16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
  • Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
  • UART Interface
  • I2C Interface
  • 16 GPIO Pins
  • SPI Interface
  • Sixteen 64-Bit Timers
  • Three On-Chip PLLsv
  • One TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.25GHz
    • 40 GMAC/20 GFLOP @ 1.2GHz
    • 32KB L1P, 32KB L1D, 512KB L2
    • 1 MB Shared L2
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessors- Packet Accelerator, Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
  • 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
  • 16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
  • Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
  • UART Interface
  • I2C Interface
  • 16 GPIO Pins
  • SPI Interface
  • Sixteen 64-Bit Timers
  • Three On-Chip PLLsv

The TMS320C6671 Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with the C66x CorePac DSP runing at 1.0 to 1.25 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6671 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

The TMS320C6671 Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with the C66x CorePac DSP runing at 1.0 to 1.25 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6671 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

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Technical documentation

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Type Title Date
* Data sheet TMS320C6671 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. E) 07 May 2014
* Errata TMS320C6671 Multicore Fixed and Floating-Point DSP Errata (Revs 1.0, 2.0) (Rev. H) 29 Jun 2015
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 07 Jul 2022
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 25 Jun 2021
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 May 2021
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 17 May 2019
Application note Hardware Design Guide for KeyStone Devices (Rev. D) 21 Mar 2019
Application note KeyStone I DDR3 interface bring-up 06 Mar 2019
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14 Aug 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26 Jul 2017
Application note KeyStone I DDR3 Initialization (Rev. E) 28 Oct 2016
Application note SERDES Link Commissioning on KeyStone I and II Devices 13 Apr 2016
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 06 May 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 09 Apr 2015
User guide DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) 20 Jan 2015
Application note TI Keystone DSP Hyperlink SerDes IBIS-AMI Models 09 Oct 2014
Application note TI Keystone DSP PCIe SerDes IBIS-AMI Models 09 Oct 2014
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04 Sep 2014
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 03 Sep 2014
More literature KeyStone Lab Manual - Training 05 Jun 2014
User guide System Analyzer User's Guide (Rev. F) 18 Nov 2013
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30 Sep 2013
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 15 Jul 2013
White paper Another Look at the Future of Medical Processing 12 Jul 2013
White paper Medical Software Development on Keystone Devices 12 Jul 2013
White paper Accelerating high-performance computing development with Desktop Linux SDK 08 Jul 2013
User guide Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D) 03 Jul 2013
User guide C66x CorePac User's Guide (Rev. C) 28 Jun 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28 Jun 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 28 May 2013
User guide Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B) 05 Feb 2013
Product overview OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 05 Nov 2012
Application note SerDes Implementation Guidelines for KeyStone I Devices 31 Oct 2012
Product overview TMS320C66x high-performance multicore DSPs for video surveillance 06 Sep 2012
Application note Multicore Programming Guide (Rev. B) 29 Aug 2012
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 21 Aug 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 21 Aug 2012
User guide Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A) 11 Jul 2012
White paper Leveraging multicore processors for machine vision applications 09 May 2012
User guide Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) 24 Apr 2012
Product overview TMS320C6678 Multicore DSP for Multimedia Infrastructure (Rev. A) 11 Apr 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30 Mar 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27 Mar 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22 Mar 2012
White paper Maximizing Multicore Efficiency with Navigator Runtime 23 Feb 2012
White paper Comparing TI's TMS320C6671 DSP with ADI’s ADSP-TS201S TigerSHARC Processor (Rev. A) 06 Jan 2012
Application note PCIe Use Cases for KeyStone Devices 13 Dec 2011
User guide Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) 15 Oct 2011
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide Debug and Trace for KeyStone I Devices User's Guide (Rev. A) 22 Sep 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02 Sep 2011
White paper KeyStone Multicore SoC Tool Suite: one platform for all needs 17 Jun 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24 May 2011
Product overview TMS320C6671/72/74/78 High-Performance Multicore Fixed- and Floating-Point DSPs (Rev. B) 25 Apr 2011
Application note TMS320C66x DSP Generation of Devices (Rev. A) 25 Apr 2011
White paper KeyStone Memory Architecture White Paper (Rev. A) 21 Dec 2010
User guide C66x CPU and Instruction Set Reference Guide 09 Nov 2010
User guide C66x DSP Cache User's Guide 09 Nov 2010
Application note Clocking Design Guide for KeyStone Devices 09 Nov 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09 Nov 2010
Application note Optimizing Loops on the C66x DSP 09 Nov 2010
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 09 Nov 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09 Nov 2010
User guide Network Coprocessor for KeyStone Devices User's Guide 02 Nov 2010

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